1. Field of the Invention
The present invention relates to a phase difference signal generator and a multi-phase clock signal generator using the phase difference signal generator.
2. Description of the Related Art
Recently, integrated circuit devices have led to an increase in the clock frequency for the operation thereof. The maximum frequency of a clock signal generated by an oscillator is limited by the performance of the devices. In order to overcome this limitation of frequency, phase difference signal generators have been developed.
In a first prior art phase difference signal generator (see: Stefanos Sidiropoulos, xe2x80x9cA Semidigital Dual Delay-Locked Loopxe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, pp. 1683-1692, November 1997 and JP-A-10-171548), a delay line is constructed by delay elements connected in series. In this case, the delay time of the delay elements is definite and is adjusted by a delay line control unit. Thus, phase difference signals having a phase of, e.g. 30xc2x0 different from each other are obtained. This will be explained later in detail.
In the above-described first prior art phase difference signal generator, however, a fine feedback control by the delay line control unit requires a complex circuit design, thus increasing the manufacturing cost. Also, the phase difference signal generator is large in size and has high power consumption.
In a second prior art phase difference signal generator (see: Japanese Utilility Model Publication No. 57-34729), a carrier wave oscillator, D-type flip-flops and the like are provided. As a result, the carrier wave oscillator has a frequency twice that of the obtained phase difference signals. This will be explained later in detail.
In the above-described second prior art phase difference signal generator, however, the frequency of the phase difference signals is half of that of the carrier wave oscillator, which is a problem.
In a third prior art phase difference signal generator (see JP-A-63-121307), when a first distributor receives an input clock signal, the first distributor transmits it to a second distributor connected to an inverter and also transmits it via a delay circuit to a third distributor. A first adder adds an output signal of the second distributor to an output signal of the third distributor to generate a first phase difference signal. On the other hand, a second adder adds an output signal of the second distributor to an output signal of the third distributor to generate a second phase difference signal having a phase of 90xc2x0 relative to the first phase difference signal. This also will be explained later in detail.
In the above-described third prior art phase difference signal generator, however, one of the first and second phase difference signals has a smaller amplitude, which would not operate a post stage circuit.
It is an object of the present invention to provide a phase difference signal generator which requires no complex feedback control, can generate larger frequency phase difference signals and can suppress the decrease of amplitude thereof.
Another object is to provide a multi-phase clock signal generator using such a phase difference signal generator.
According to the present invention, in a phase difference signal generator, a first delay circuit has a delay time of nx where n is 2, 3, . . . and x is a voluntary real number. The first delay circuit receives a first input clock signal having a phase of 0xc2x0 to generate a first phase difference signal. At least one k-to-(nxe2x88x92k) weighted phase interpolator has a first input for receiving an output signal of the first delay circuit and a second input for receiving a second input clock signal having a phase of xcex8 to generate an output signal having a phase of (nxe2x88x92k)x+kxcex8/n where k is 1, 2, . . . , nxe2x88x921. At least one second delay circuit is connected to the k-to-(nxe2x88x92k) weighted phase interpolator. The second delay circuit has a delay time of kx to generate a k-th phase difference signal.